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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16655
240-OUTPUT TFT-LCD GATE DRIVER
The PD16655 is a TFT-LCD gate driver equipped with 240-output lines. It can output a high-gate scanning voltage in response to 5 V/3.3 V CMOS level input because it provided with a level-shift circuit as a logic-input circuit. This gate driver is also provided with an output enable (OE) function, so that drivers can be installed at both sides.
FEATURES
* * * * * * * High-output voltage (VDD-VEE = amplitude: 31 V MAX.) Shift-direction select function Level shift of negative voltage VEE2(level shift range: VDD-VEE2 = 15 V) 5 V/3.3 V CMOS level interface Output enable function As many as 240-output lines Slim TCP
ORDERING INFORMATION
Part Number Package TCP(TAB package)
PD16655N-xxx
Remark The TCP's external shape is custom model. To order your TCP's external shape, please contact a NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S11950EJ2V0DS00 (2nd edition) Date Published February 1999 NS CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1998
PD16655
1. BLOCK DIAGRAM
R,/L
LSNote
CLK
LSNote
STVR
LSNote SR1 SR2 SR3
240-bit shift register SR238 SR239 SR240
LSNote
STVL
OE
LSNote
VEE1 VEE2 O1 O2 O3 O238 O239 O240
Note LS (level shifter): Shifts 5 V/3.3 V CMOS level and VDD2-VEE1 level. Remark /xxx indicates active low signal.
2
Data Sheet S11950EJ2V0DS00
PD16655
2. PIN CONFIGURATION ( PD16655N-xxx)
O240 O239 VDD2 VDD1 STVL OE CLK R,/L VCC VSS STVR VEE1 VEE2 O3 O2 O1 Copper foil surface O238
Remark This figure does not specify the TCP package.
Data Sheet S11950EJ2V0DS00
3
PD16655
3. PIN FUNCTIONS
SYMBOL O1 to O240 PIN NAME Driver Output I/O DESCRIPTION These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD. The output signals change in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 - VEE2. VSS/VCC or VDD1/VEE1 (input) This is the input of the internal shift register. The input date is read at the rising edge of shift clock CLK, and scan signals are output from the O1 through O120 pins. The input level is a VCC/VSS or VDD1 - VEE1 level. This pin outputs a start pulse to the PD16655 at the next stage when two or more PD16655s are connected in cascade. The pulse is output at the falling edge of the 240th clock of shift clock CLK, and is cleared at the falling edge of the 241st clock. R,/L = "H" (right shift): STVR O1 O240 STVL R,/L = "L" (left shift): STVL O240 O1 STVR This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input. When this pin goes "H", the driver output is fixed to "L". The shift register is not cleared, however. The internal logic operates even when OE = "H". OE is in asynchronization with the clock. 10 V to 25 V 10 V to 25 V 3.0 to 5.5 V Reference voltage to level shifter LS.
STVR STVL
Start Pulse Input/Output
VDD1/VEE1 (output)
R,/L
Shift Direction Select Input
VSS/VCC or VDD1/VEE1 VSS/VCC
CLK
Shift Clock Input
OE
Output Enable Input
VSS/VCC
VDD1 VDD2 VCC
Logic Positive Power Supply Driver Positive Power Supply Reference Positive Power Supply Reference Negative Power Supply Logic Negative Power Supply Driver Negative Power Supply
VSS
Connect this pin to the ground of the system.
VEE1 VEE2
-21 V to -3 V -21 V to VDD2 - 15 V
Cautions 1. To prevent latch up, turn on power to VCC, VEE1-VEE2, VDD1-VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period.
2. Insert a capacitor of about 0.1 F between each power line, as shown below, to secure noise margin such as VIH and VIL, because the internal logic operates on a high voltage level. (VDD = VDD1 = VDD2)
VDD VCC 0.1 F VSS 0.1 F VEE 0.1 F
4
Data Sheet S11950EJ2V0DS00
PD16655
3. In an application where the VEE power supply is not shifted, short-circuit VEE2 (driver power) and VEE1 (logic power) outside the TCP. Fix unused pins to the VEE level. 4. The level shift range of VEE2 must be VEE1 VEE2 VDD - 15 V. Note that, in this case, the guaranteed values of the output ON resistance and output fall time slightly change. (VDD = VDD1 = VDD2)
5. TIMING CHART
1 CLK
2
3
239
240
241
242
STVR (STVL)
O1
O2
O3
O239
O240
STVL (STVR)
O1 of next stage
O2 of next stage
Caution Do not use a sequence in which the outputs change all at once because such a sequence may cause malfunctioning.
Data Sheet S11950EJ2V0DS00
5
PD16655
6. ELECTRICAL SPECIFICATION
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Logic Positive Supply Voltage Driver Positive Supply Voltage Reference Positive Power Supply Voltage Power Supply Voltage Symbol VDD1 VDD2 VCC VDD1-VEE1 VDD2-VEE2 VEE1 VEE2 VI II IO TA Tstg Ratings -0.5 to +28 -0.5 to +28 -0.5 to +7 -0.5 to +33 Unit V V V V
Logic Negative Supply Voltage Driver Negative Supply Voltage Input Voltage Input Current Output Current Operating Temperature Range Storage Temperature Range
-23 to +0.5 -23 to +0.5 VEE1 - 0.5 to VDD1 + 0.5 10 10 -30 to +85 -55 to +125
V V V mA mA C C
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = -30 to 85C, VSS = 0 V)
Parameter Logic Positive Supply Voltage Driver Positive Supply Voltage Logic Negative Supply Voltage Driver Negative Supply Voltage Power Supply Voltage Symbol VDD1 VDD2 VEE1 VEE2 VDD1-VEE1 VDD2-VEE2 VCC MIN. 10 10 -21 -21 15 TYP. MAX. 25 25 -3 VDD2 - 15 31 Unit V V V V V
Reference Positive Power Supply Voltage
2.7
5.5
V
Caution Observe the following condition when shifting VEE2 (driver power). Note that, in this case, the guaranteed values of the output ON resistance and output fall time slightly change. VEE1 VEE2 VDD - 15 V (VDD1 or VDD2)
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Data Sheet S11950EJ2V0DS00
PD16655
ELECTRICAL CHARACTERISTICS (TA = -30 to +85 C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = -9 V, VSS = 0 V, VCC = 2.7 V or 5.5 V)
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Output Driver Current Low-Level Output Driver Current Symbol VIH VIL VOH VOL IXOH STVR-STVL, without load STVR-STVL, without load Driver output, VO = VDD2 - 1.0 V Condition MIN 0.7 VCC VEE1 VDD1 - 0.05 VEE1 TYP. MAX. VDD1 0.3 VCC VDD1 VEE1 + 0.05 -2.0 Unit V V V V mA
IXOL1 IXOL2
Driver output, VO = VEE2 + 1.0 V Driver output, VO = VEE2 + 1.0 V, VEE2 = VDD - 15 V
2.0 1.5
mA mA
LCD Driver Output ON Resistance
RON1 RON2
VO = VEE2 + 1.0 V, VDD2 - 1.0 V VO = VEE2 + 1.0 V, VDD2 - 1.0 V, VEE2 = VDD - 15 V
500 700

High-Level Output Pulse Current Low-Level Output Pulse Current Input Leak Current Static Current Dissipation
IPOH
STVR-STVL, VO = VDD1 - 1.0 V
-2.0
mA
IPOL
STVR-STVL, VO = VEE1 + 1.0 V
2.0 1 400 -400 800 -800 50
mA
IIL IDD IEE ICC
VI = 0 V or 3 V or 5 V VDD1, VDD2 pin, fCLK = 31.5 kHz VEE1, VEE2 pin, fCLK = 31.5 kHz VCC pin, fCLK = 31.5 kHz
A A A A
Data Sheet S11950EJ2V0DS00
7
PD16655
SWICHING CHARACTERISTICS (TA = -30 to +85 C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = -9 V, VSS = 0 V, VCC = 2.7 V to 5.5 V)
Parameter Cascade Output Delay Time Symbol tPHL1 tPLH1 Driver Output Delay Time tPHL2 tPLH2 td1 td2 Output Rise Time Output Fall Time tTLH tTHL1 tTHL2 Input Capacitance Clock Frequency CI fCLK CL = 220 pF CLK Xon CL = 220 pF, OE: L H CL = 220 pF, OE: H L CL = 220 pF CL = 220 pF CL = 220 pF, VEE2 = VDD - 15 V TA = 25C In cascade connection 100 CL = 20 pF Condition MIN. TYP. MAX. 600 600 700 700 700 700 300 300 400 15 Unit ns ns ns ns ns ns ns ns ns pF kHz
TIMING REQUIREMENTS (TA = -30 to 85 C, VDD1 = VDD2 = 22 V, VEE1 = VEE2 = -9 V, VSS = 0 V, VCC = 2.7 V to 5.5 V)
Parameter Clock Pulse Width Data Setup Time Data Hold Time Symbol PWCLK tsetup thold STVR(STVL) CLK CLK STVR(STVL) Condition MIN. 1000 100 100 TYP. MAX. Unit ns ns ns
Caution
Keep the time and fall time of the logic input to tr = tf = 20 ns (10 to 90 % of the rated values).
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Data Sheet S11950EJ2V0DS00
PWCLK tr 90% 2 4 5 6 7 237 238 239 240 3
tf
CLK
1
10%
tSETUP tHOLD
STVR
tPLH2
tPHL2
O1 90% tTHL
O2
* * *
10% tTLH
7. SWITCHING CHARACTERISTIC WAVEFORM
O239
O240 tPLH1 tPHL1
Data Sheet S11950EJ2V0DS00
STVL
OE
td1
td2
O1-240
PD16655
9
PD16655
8. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for mounting conditions of the PD16655. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16655N-xxx : TCP(TAB package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C, heating for 2 to 3 seconds: pressure 100 g (per solder) Temporary bonding 70 to 100C; pressure 3 to 8 kg/cm ; time 3 to 5 secs. 2 Real bonding 165 to 180C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
2
ACF (Adhesive Conductive Film)
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
10
Data Sheet S11950EJ2V0DS00
PD16655
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S11950EJ2V0DS00
11
PD16655
Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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